Intel Arria 10 - Page 348

Figure 168. Arria 10 PLLs and Clock Networks
Local CGB
CDR
CH2
Local CGB
CDR/CMU
CH1
Local CGB
CDR
CH0
fPLL
ATX
PLL
Master
CGB
Local CGB
CDR
CH5
Local CGB
CDR/CMU
CH4
Local CGB
CDR
CH3
fPLL
ATX
PLL
Master
CGB
Local CGB
CDR
CH2
Local CGB
CDR/CMU
CH1
Local CGB
CDR
CH0
fPLL
ATX
PLL
Master
CGB
x1 Clock Lines x6 Clock Lines xN Clock Lines
Transceiver
Bank
Transceiver
Bank
Related Information
• Channel Bonding on page 389
• Device Transceiver Layout on page 9
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
348