Intel Arria 10 User Manual

When in core mode, for the fPLL to generate output clocks with a fixed frequency and
phase relation to an input reference clock, the Enable phase alignment option must
be selected. In the fractional frequency mode, the fPLL supports data rates from 1
Gbps to 12.5 Gbps.
Input Reference Clock
This is the dedicated input reference clock source for the PLL.
The input reference clock can be sourced from one of the following:
• Dedicated reference clock pin
• Reference clock network
• Receiver input pin
• Output of another PLL with PLL cascading
• Global clock or the core clock network
The input reference clock is a differential signal. Intel recommends using the
dedicated reference clock pin as the input reference clock source for best jitter
performance. For protocol jitter compliance at data rates > 10 Gbps, Intel
recommends using the dedicated reference clock pin in the same triplet with the fPLL
as the input reference clock source.The input reference clock must be stable and free-
running at device power-up for proper PLL operation. If the reference clock is not
available at device power-up, then you must recalibrate the PLL when the reference
clock is available.
Note: Sourcing reference clock from a cascaded PLL output, global clock or core clock
network introduces additional jitter to the fPLL output. Refer to KDB "How do I
compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL
reference clock?" for more details.
The fPLL calibration is clocked by the CLKUSR clock, which must be stable and
available for the calibration to proceed. Refer to the Calibration on page 567 section
for details about PLL calibration and CLKUSR clock.
Reference Clock Multiplexer
The refclk mux selects the reference clock to the PLL from the various available
reference clock sources.
N Counter
The N counter divides the reference clock (refclk) mux's output. The N counter
division helps lower the loop bandwidth or reduce the frequency within the phase
frequency detector's (PFD) operating range. The N counter supports division factors
from 1 to 32.
Phase Frequency Detector
The reference clock (refclk) signal at the output of the N counter block and the
feedback clock (fbclk) signal at the output of the M counter block are supplied as an
inputs to the PFD. The output of the PFD is proportional to the phase difference
between the refclk and fbclk inputs. The PFD aligns the fbclk to the refclk.
The PFD generates an "Up" signal when the reference clock's falling edge occurs
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex