Intel Arria 10 User Manual

Parameters Range Description
MCGB input clock frequency Read only Displays the master CGB’s required input clock frequency.
You cannot set this parameter.
MCGB output data rate Read only Displays the master CGB’s output data rate. You cannot set
this parameter.
This value is calculated based on MCGB input clock
frequency and MCGB clock division factor.
Enable bonding clock output ports On/Off
Enables the tx_bonding_clocks output ports of the
Master CGB used for channel bonding.
You must enable this parameter for bonded designs.
Enable feedback compensation
bonding
On/Off Enables the feedback output path of the master CGB used
for feedback compensation bonding. When enabled, the
feedback connections are automatically handled by the PLL
IP.
PMA interface width 8, 10, 16, 20,
32, 40, 64
Specifies the PMA-PCS interface width.
Match this value with the PMA interface width selected for
the Native PHY IP core. You must select a proper value for
generating bonding clocks for the Native PHY IP core.
Table 236. fPLL—Dynamic Reconfiguration Parameters and Settings
Parameter Range Description
Enable reconfiguration On/Off Enables the PLL reconfiguration interface. Enables the
simulation models and adds more ports for reconfiguration.
Enable Altera Debug Master
Endpoint
On/Off When you turn this option ON, the transceiver PLL IP core
includes an embedded Altera Debug Master Endpoint
(ADME) that connects internally to the Avalon-MM slave
interface for dynamic reconfiguration. The ADME can access
the reconfiguration space of the transceiver. It can perform
certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
Separate reconfig_waitrequest
from the status of AVMM
arbitration with PreSICE
On/Off
When enabled, the reconfig_waitrequest does not
indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status is reflected in a soft status register
bit. (Only available if "Enable control and status registers
feature" is enabled).
Enable capability registers On/Off Enables capability registers that provide high-level
information about the fPLL's configuration.
Set user-defined IP identifier Sets a user-defined numeric identifier that can be read from
the user_identifier offset when the capability registers
are enabled.
Enable control and status registers On/Off Enables soft registers for reading status signals and writing
control signals on the PLL interface through the embedded
debug logic.
Configuration file prefix Enter the prefix name for the configuration files to be
generated.
Generate SystemVerilog package
file
On/Off Generates a SystemVerilog package file containing all
relevant parameters used by the PLL.
Generate C header file On/Off Generates a C header file containing all relevant parameters
used by the PLL.
Generate MIF (Memory Initialize
File)
On/Off Generates a MIF file that contains the current configuration.
Use this option for reconfiguration purposes in order to
switch between different PLL configurations.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
364

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex