Intel Arria 10 User Manual

Port Direction Clock Domain Description
pll_refclk2 input N/A Reference clock input port 2.
pll_refclk3 input N/A Reference clock input port 3.
pll_refclk4 input N/A Reference clock input port 4.
tx_serial_clk output N/A High speed serial clock output port
for GX channels. Represents the x1
clock network.
pll_locked output Asynchronous Active high status signal which
indicates if PLL is locked.
hssi_pll_cascade_clk output N/A fPLL cascade clock output port
pll_pcie_clk output N/A Used for PCIe.
reconfig_clk0 input N/A Optional Avalon interface clock. Used
for PLL reconfiguration.
reconfig_reset0 input reconfig_clk0 Used to reset the Avalon interface.
Asynchronous to assertion and
synchronous to deassertion.
reconfig_write0 input reconfig_clk0 Active high write enable signal.
reconfig_read0 input reconfig_clk0 Active high read enable signal.
reconfig_address0[9:0] input reconfig_clk0 10-bit address bus used to specify
address to be accessed for both read
and write operations.
reconfig_writedata0[31:0] input reconfig_clk0 32-bit data bus. Carries the write
data to the specified address.
reconfig_readdata0[31:0] output reconfig_clk0 32-bit data bus. Carries the read
data from the specified address.
reconfig_waitrequest0
output reconfig_clk0 Indicates when the Avalon interface
signal is busy. When asserted, all
inputs must be held constant.
pll_cal_busy output Asynchronous Status signal which is asserted high
when PLL calibration is in progress.
Perform logical OR with this signal
and the tx_cal_busy port on the
reset controller IP.
mcgb_rst input Asynchronous Master CGB reset control.
Deassert this reset at the same time
as pll_powerdown .
mcgb_aux_clk0 input N/A Used for PCIe to switch between
fPLL/ATX PLL during link speed
negotiation.
tx_bonding_clocks[5:0] output N/A Optional 6-bit bus which carries the
low speed parallel clock outputs from
the Master CGB.
Used for channel bonding, and
represents the x6/xN clock network.
mcgb_serial_clk output N/A High speed serial clock output for
x6/xN non-bonded configurations.
pcie_sw[1:0] input Asynchronous 2-bit rate switch control input used
for PCIe protocol implementation.
continued...
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
366

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex