Intel Arria 10 User Manual

Port Direction Clock Domain Description
pcie_sw_done[1:0] output Asynchronous 2-bit rate switch status output used
for PCIe protocol implementation.
atx_to_fpll_cascade_clk input N/A Enables fPLL to ATX PLL cascading
clock input port.
fpll_to_fpll_cascade_clk
output N/A fPLL to fPLL cascade output port
(only in Core mode)
active_clk
output N/A Creates an output signal that
indicates the input clock being used
by the PLL. A logic Low on this signal
indicates refclk0 is being used and
a logic High indicates refclk1 is
being used (only in Core mode with
Clock Switchover enabled)
outclk0 output N/A Core output clock 0. (only in Core
mode)
There are four core fPLL output clock
output ports. The number of output
clock available depends on the
Selected reference clock source
outclk1 output N/A Core output clock 1. (only in Core
mode)
outclk2 output N/A Core output clock 2. (only in Core
mode)
outclk3 output N/A Core output clock 3. (only in Core
mode)
ext_lock_detect_clklow
(57)
output N/A Clklow output for external lock
detection. It can be exposed by
selecting the Enable clklow and
fref port.
ext_lock_detect_fref
(57)
output N/A Fref output for external lock
detection It can be exposed by
selecting the Enable clklow and
fref port.
phase_reset input N/A Dynamic phase shift reset input
signal. To be connected to DPS soft
IP phase_reset output.
phase_en input N/A Dynamic phase shift enable input
signal. To be connected to DPS soft
IP phase_en output.
updn input N/A Dynamic phase shift updn input
signal. To be connected to DPS soft
IP updn output.
cntsel[3:0] input N/A Dynamic phase shift counter bus. To
be connected to DPS soft IP cntsel
output bus.
Related Information
• Calibration on page 29
• Reconfiguration Interface and Dynamic Reconfiguration on page 502
(57)
The fPLL fref and clklow signals should only be used with the Intel external soft lock
detection logic.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
367

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex