Intel Arria 10 User Manual

networks in the FPGA core. If the Global Signal is set to Off, it does not choose any of
the previously mentioned clock networks. Instead, it chooses directly from the local
routing between transceiver and FPGA fabric.
The transmitter channel forwards a parallel output clock tx_clkout to the FPGA
fabric to clock the transmitter data and control signals. The receiver channel forwards
a parallel output clock rx_clkout to the FPGA fabric to clock the data and status
signals from the receiver into the FPGA fabric. Based on the receiver channel
configuration, the parallel output clock is recovered from either the receiver serial data
or the rx_clkout clock (in configurations without the rate matcher) or the
tx_clkout clock (in configurations with the rate matcher).
Figure 180. FPGA Fabric - Transceiver Interface Clocking
Input Reference Clock
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
/2, /4
/2, /4
Parallel and Serial Clocks
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB)
tx_coreclkin
rx_coreclkin
rx_clkout or
tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
tx_clkout
tx_clkout
tx_clkout
rx_clkout
PRBS
Verifier
tx_pma_div_clkout
CMU PLL /
ATX PLL /
fPLL
/66
/40
/33
/2
Serializer
tx_pma_div_clkout
Serial Clock
(from CGB)
tx_clkout
/66
/40
/33
/2
Deserializer
rx_pma_div_clkout
rx_clkout
Parallel Clock
Serial Clock
Parallel and Serial Clocks
CDR Recovered
Clock
The divided versions of the tx_clkout and rx_clkout are available as
tx_pma_div_clkout and rx_pma_div_clkout, respectively.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
385

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English