Intel Arria 10 User Manual

Figure 186. PLL Feedback and Cascading Clock Network
PLL Feedback and Cascading Clock Network
fPLL1
fbclk
refclk
C
ATX PLL 1
refclk
fbclk
Master CGB1
fPLL0
refclk
fbclk
C
ATX PLL 0
refclk
fbclk
Master CGB0
Bidirectional
Tristate Buffer
Bidirectional
Tristate Buffer
0 1 2 3
refclk Lines
fbclk Lines
C, M, and CGB Outputs
Legend
Transceiver Bank
PLL Cascading
PLL Feedback Compensation Bonding
Connection (1)
Connection (3)
Connection (2)
Connection (4)
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
394

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex