Intel Arria 10 - Page 394

Figure 186. PLL Feedback and Cascading Clock Network
PLL Feedback and Cascading Clock Network
fPLL1
fbclk
refclk
C
ATX PLL 1
refclk
fbclk
Master CGB1
fPLL0
refclk
fbclk
C
ATX PLL 0
refclk
fbclk
Master CGB0
Bidirectional
Tristate Buffer
Bidirectional
Tristate Buffer
0 1 2 3
refclk Lines
fbclk Lines
C, M, and CGB Outputs
Legend
Transceiver Bank
PLL Cascading
PLL Feedback Compensation Bonding
Connection (1)
Connection (3)
Connection (2)
Connection (4)
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
394