Intel Arria 10 User Manual

Parameter Value Description
Enable datapath and
interface
reconfiguration
On/Off When you turn this option on, you can preconfigure and
dynamically switch between the Standard PCS, Enhanced PCS, and
PCS direct datapaths.
The default value is Off.
Enable simplified data
interface
On/Off
By default, all 128-bits are ports for the tx_parallel_data and
rx_parallel_data buses are exposed. You must understand the
mapping of data and control signals within the interface. Refer to
the Enhanced PCS TX and RX Control Ports section for details
about mapping of data and control signals.
When you turn on this option, the Native PHY IP core presents a
simplified data and control interface between the FPGA fabric and
transceiver. Only the sub-set of the 128-bits that are active for a
particular FPGA fabric width are ports.
The default value is Off.
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Provide separate
interface for each
channel
On/Off When selected the Native PHY IP core presents separate data,
reset and clock interfaces for each channel rather than a wide bus.
Table 10. Transceiver Configuration Rule Parameters
Transceiver Configuration Setting Description
Basic/Custom (Standard PCS) Enforces a standard set of rules within the Standard PCS. Select these rules to
implement custom protocols requiring blocks within the Standard PCS or
protocols not covered by the other configuration rules.
Basic/Custom w /Rate Match
(Standard PCS)
Enforces a standard set of rules including rules for the Rate Match FIFO within
the Standard PCS. Select these rules to implement custom protocols requiring
blocks within the Standard PCS or protocols not covered by the other
configuration rules.
CPRI (Auto) Enforces rules required by the CPRI protocol. The receiver word aligner mode is
set to Auto. In Auto mode, the word aligner is set to deterministic latency.
CPRI (Manual) Enforces rules required by the CPRI protocol. The receiver word aligner mode is
set to Manual. In Manual mode, logic in the FPGA fabric controls the word
aligner.
GbE Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.
GbE 1588 Enforces rules for the 1 GbE protocol with support for Precision time protocol
(PTP) as defined in the IEEE 1588 Standard.
Gen1 PIPE Enforces rules for a Gen1 PCIe
®
PIPE interface that you can connect to a soft
MAC and Data Link Layer.
Gen2 PIPE Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC
and Data Link Layer.
Gen3 PIPE Enforces rules for a Gen3 PCIe PIPE interface that you can connect to a soft MAC
and Data Link Layer.
Basic (Enhanced PCS) Enforces a standard set of rules within the Enhanced PCS. Select these rules to
implement protocols requiring blocks within the Enhanced PCS or protocols not
covered by the other configuration rules.
Interlaken Enforces rules required by the Interlaken protocol.
10GBASE-R Enforces rules required by the 10GBASE-R protocol.
continued...
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This option cannot be used, if you intend to dynamically reconfigure between PCS datapaths,
or reconfigure the interface of the transceiver.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
50

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex