Intel Arria 10 - Page 508

The MIF file and C header file are set up similarly to the SystemVerilog package file.
Multiple transceiver features may reside at the same address. Also, a single
transceiver feature may span across multiple addresses.
Dynamic reconfiguration requires at least two configurations of the Transceiver Native
PHY IP core or PLL IP core. One configuration defines the base transceiver or PLL
configuration and the other configurations define the modified or target configurations.
Use the IP Parameter Editor to create base and modified configurations of the
Transceiver Native PHY or PLL IP core, according to the following table.
Table 264. Transceiver Native PHY or PLL IP Parameters (Base and Modified
Configurations)
Native PHY or PLL
Instance
Required Parameter Settings Saved In
Base Configuration •
Click Interfaces ➤ Transceiver PHY ➤ Arria 10
Transceiver Native PHY for the Native PHY IP
core. Or, select one of the supported transmit PLL IP
cores under PLL. Enable all options required for the
base configuration, such as data rate, PCS options,
and PMA options.
• Enable all ports to be used by the modified
configuration. For example, if the bitslip feature is
not required in the base configuration, but required
in modified configuration, then you must enable the
tx_std_bitslipboundarysel port. Reconfiguring
between Standard PCS, Enhanced PCS, and PCS
Direct requires that you turn on Enable datapath
and interface reconfiguration. The Transceiver
configuration rules define the initial mode of the
PHY instance.
• On the Dynamic Reconfiguration tab, turn on
Enable dynamic reconfiguration and specify the
Configuration Options.
This flow requires that you turn on Configuration file
option.
•
<Native PHY Base Instance Name>/
reconfig/
altera_xcvr_native_a10_reconf
ig_parameters.sv contains all
transceiver register addresses and
their bit value for that transceiver
configuration.
Or
•
<PLL Base Instance Name>/
reconfig/
altera_xcvr_<type>_pll_a10_re
config_parameters.sv contains
all PLL register addresses and their bit
value for that PLL configuration.
Modified
Configuration
•
Click Interfaces ➤ Transceiver PHY ➤ Arria 10
Transceiver Native PHY. Or, select one of the
supported transmit PLL IP cores under PLL. Enable
all options required for the modified configuration,
such as data rate, PCS options, and PMA options.
• Enable all ports that are used by the modified
configuration. Reconfiguring between Standard PCS,
Enhanced PCS, and PCS Direct requires Enable
datapath and interface reconfiguration be
enabled. The Transceiver configuration rules
define the mode of the PHY instance.
• On the Dynamic Reconfiguration tab, turn on
Enable dynamic reconfiguration and specify the
same Configuration Options as the base instance.
• <Native PHY Modified Instance
Name>/reconfig/
altera_xcvr_native_a10_reconf
ig_parameters.sv contains all
transceiver register addresses and
their bit value for that transceiver
configuration.
Or
•
<PLL Modified Instance Name>/
reconfig/
altera_xcvr_<type>_pll_a10_re
config_parameters.sv contains
all PLL register addresses and their bit
value for that PLL configuration.
Note: You can generate the base and modified configuration files in the same or different
folders. If you use the same folder, each configuration name must be unique.
Intel recommends following the flow described in the Steps to Perform Dynamic
Reconfiguration section when performing dynamic reconfiguration of either the Native
PHY IP core or transmit PLL IP core.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 516
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
508