Intel Arria 10 User Manual

Parameter Range Description
Enable tx_enh_frame
port
On / Off
Enables the tx_enh_frame status output port. When the
Interlaken frame generator is enabled, this signal indicates the
beginning of a new metaframe. This is an asynchronous signal.
Enable
tx_enh_frame_diag_st
atus port
On / Off
Enables the tx_enh_frame_diag_status 2-bit input port.
When the Interlaken frame generator is enabled, the value of this
signal contains the status message from the framing layer
diagnostic word. This signal is synchronous to tx_clkout.
Enable
tx_enh_frame_burst_e
n port
On / Off
Enables the tx_enh_frame_burst_en input port. When burst
control is enabled for the Interlaken frame generator, this signal is
asserted to control the frame generator data reads from the TX
FIFO. This signal is synchronous to tx_clkout.
Table 21. Interlaken Frame Synchronizer Parameters
Parameter Range Description
Enable Interlaken
frame synchronizer
On / Off When you turn on this option, the Enhanced PCS frame
synchronizer is enabled.
Frame synchronizer
metaframe length
5-8192 Specifies the metaframe length of the frame synchronizer.
Enable rx_enh_frame
port
On / Off Enables the rx_enh_frame status output port. When the
Interlaken frame synchronizer is enabled, this signal indicates the
beginning of a new metaframe. This is an asynchronous signal.
Enable
rx_enh_frame_lock
port
On / Off Enables the rx_enh_frame_lock output port. When the
Interlaken frame synchronizer is enabled, this signal is asserted to
indicate that the frame synchronizer has achieved metaframe
delineation. This is an asynchronous output signal.
Enable
rx_enh_frame_diag_st
atus port
On / Off Enables therx_enh_frame_diag_status output port. When the
Interlaken frame synchronizer is enabled, this signal contains the
value of the framing layer diagnostic word (bits [33:32]). This is a
2 bit per lane output signal. It is latched when a valid diagnostic
word is received. This is an asynchronous signal.
Table 22. Interlaken CRC32 Generator and Checker Parameters
Parameter Range Description
Enable Interlaken TX
CRC-32 Generator
On / Off When you turn on this option, the TX Enhanced PCS datapath
enables the CRC32 generator function. CRC32 can be used as a
diagnostic tool. The CRC contains the entire metaframe including
the diagnostic word.
Enable Interlaken TX
CRC-32 generator
error insertion
On / Off When you turn on this option, the error insertion of the interlaken
CRC-32 generator is enabled. Error insertion is cycle-accurate.
When this feature is enabled, the assertion of tx_control[8] or
tx_err_ins signal causes the CRC calculation during that word is
incorrectly inverted, and thus, the CRC created for that metaframe
is incorrect.
Enable Interlaken RX
CRC-32 checker
On / Off Enables the CRC-32 checker function.
Enable
rx_enh_crc32_err port
On / Off When you turn on this option, the Enhanced PCS enables the
rx_enh_crc32_err port. This signal is asserted to indicate that
the CRC checker has found an error in the current metaframe.
This is an asynchronous signal.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
59

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex