Intel Arria 10 User Manual

Parameter Range Description
Enable RX FIFO control
word deletion
(Interlaken)
On / Off When you turn on this option, Interlaken control word removal is
enabled. When the Enhanced PCS RX FIFO is configured in
Interlaken mode, enabling this option, removes all control words
after frame synchronization is achieved. Enabling this option
requires that you also enable alignment word deletion.
Enable
rx_enh_data_valid port
On / Off Enables the rx_enh_data_valid port. This signal indicates when
RX data from RX FIFO is valid. This signal is synchronous to
rx_coreclkin.
Enable rx_enh_fifo_full
port
On / Off Enables the rx_enh_fifo_full port. This signal indicates when
the RX FIFO is full. This is an asynchronous signal.
Enable
rx_enh_fifo_pfull port
On / Off Enables the rx_enh_fifo_pfull port. This signal indicates when
the RX FIFO has reached the specified partially full threshold. This
is an asynchronous signal.
Enable
rx_enh_fifo_empty
port
On / Off Enables the rx_enh_fifo_empty port. This signal indicates when
the RX FIFO is empty. This signal is synchronous to
rx_coreclkin.
Enable
rx_enh_fifo_pempty
port
On / Off Enables the rx_enh_fifo_pempty port. This signal indicates
when the RX FIFO has reached the specified partially empty
threshold. This signal is synchronous to rx_coreclkin.
Enable rx_enh_fifo_del
port (10GBASE-R)
On / Off Enables the optional rx_enh_fifo_del status output port. This
signal indicates when a word has been deleted from the rate
match FIFO. This signal is only used for 10GBASE-R transceiver
configuration rule. This is an asynchronous signal.
Enable
rx_enh_fifo_insert port
(10GBASE-R)
On / Off Enables the rx_enh_fifo_insert port. This signal indicates when
a word has been inserted into the rate match FIFO. This signal is
only used for 10GBASE-R transceiver configuration rule. This
signal is synchronous to rx_coreclkin.
Enable
rx_enh_fifo_rd_en port
On / Off Enables the rx_enh_fifo_rd_en input port. This signal is
enabled to read a word from the RX FIFO. This signal is
synchronous to rx_coreclkin.
Enable
rx_enh_fifo_align_val
port (Interlaken)
On / Off Enables the rx_enh_fifo_align_val status output port. Only
used for Interlaken transceiver configuration rule. This signal is
synchronous to rx_clkout.
Enable
rx_enh_fifo_align_clr
port (Interlaken)
On / Off Enables the rx_enh_fifo_align_clr input port. Only used for
Interlaken. This signal is synchronous to rx_clkout.
Table 20. Interlaken Frame Generator Parameters
Parameter Range Description
Enable Interlaken
frame generator
On / Off Enables the frame generator block of the Enhanced PCS.
Frame generator
metaframe length
5-8192 Specifies the metaframe length of the frame generator. This
metaframe length includes 4 framing control words created by the
frame generator.
Enable Frame
Generator Burst
Control
On / Off Enables frame generator burst. This determines whether the
frame generator reads data from the TX FIFO based on the input
of port tx_enh_frame_burst_en.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
58

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex