Intel Arria 10 User Manual

Table 23. 10GBASE-R BER Checker Parameters
Parameter Range Description
Enable
rx_enh_highber port
(10GBASE-R)
On / Off Enables the rx_enh_highber port. For 10GBASE-R transceiver
configuration rule, this signal is asserted to indicate a bit error
rate higher than 10
-4
. Per the 10GBASE-R specification, this
occurs when there are at least 16 errors within 125 μs. This is an
asynchronous signal.
Enable
rx_enh_highber_clr_c
nt port (10GBASE-R)
On / Off Enables the rx_enh_highber_clr_cnt input port. For the
10GBASE-R transceiver configuration rule, this signal is asserted
to clear the internal counter. This counter indicates the number of
times the BER state machine has entered the "BER_BAD_SH"
state. This is an asynchronous signal.
Enable
rx_enh_clr_errblk_cou
nt port (10GBASE-R)
On / Off Enables the rx_enh_clr_errblk_count input port. For the
10GBASE-R transceiver configuration rule, this signal is asserted
to clear the internal counter. This counter indicates the number of
the times the RX state machine has entered the RX_E state. For
protocols with FEC block enabled, this signal is asserted to reset
the status counters within the RX FEC block. This is an
asynchronous signal.
Table 24. 64b/66b Encoder and Decoder Parameters
Parameter Range Description
Enable TX 64b/66b
encoder (10GBASE-R)
On / Off When you turn on this option, the Enhanced PCS enables the TX
64b/66b encoder.
Enable RX 64b/66b
decoder (10GBASE-R)
On / Off When you turn on this option, the Enhanced PCS enables the RX
64b/66b decoder.
Enable TX sync header
error insertion
On / Off When you turn on this option, the Enhanced PCS supports cycle-
accurate error creation to assist in exercising error condition
testing on the receiver. When error insertion is enabled and the
error flag is set, the encoding sync header for the current word is
generated incorrectly. If the correct sync header is 2'b01 (control
type), 2'b00 is encoded. If the correct sync header is 2'b10 (data
type), 2'b11 is encoded.
Table 25. Scrambler and Descrambler Parameters
Parameter Range Description
Enable TX scrambler
(10GBASE-R/
Interlaken)
On / Off Enables the scrambler function. This option is available for the
Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R
protocols. You can enable the scrambler in Basic (Enhanced PCS)
mode when the block synchronizer is enabled and with 66:32,
66:40, or 66:64 gear box ratios.
TX scrambler seed
(10GBASE-R/
Interlaken)
User-specified 58-bit
value
You must provide a non-zero seed for the Interlaken protocol. For
a multi-lane Interlaken Transceiver Native PHY IP, the first lane
scrambler has this seed. For other lanes' scrambler, this seed is
increased by 1 per each lane. The initial seed for 10GBASE-R is
0x03FFFFFFFFFFFFFF. This parameter is required for the
10GBASE-R and Interlaken protocols.
Enable RX descrambler
(10GBASE-R/
Interlaken)
On / Off Enables the descrambler function. This option is available for Basic
(Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You
can enable the descrambler in Basic (Enhanced PCS) mode with
the block synchronizer enabled and with 66:32, 66:40, or 66:64
gear box ratios.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
60

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex