Intel Arria 10 User Manual

Table 26. Interlaken Disparity Generator and Checker Parameters
Parameter Range Description
Enable Interlaken TX
disparity generator
On / Off When you turn on this option, the Enhanced PCS enables the
disparity generator. This option is available for the Interlaken
protocol.
Enable Interlaken RX
disparity checker
On / Off When you turn on this option, the Enhanced PCS enables the
disparity checker. This option is available for the Interlaken
protocol.
Enable Interlaken TX
random disparity bit
On / Off Enables the Interlaken random disparity bit. When enabled, a
random number is used as disparity bit which saves one cycle of
latency.
Table 27. Block Synchronizer Parameters
Parameter Range Description
Enable RX block
synchronizer
On / Off When you turn on this option, the Enhanced PCS enables the RX
block synchronizer. This options is available for the Basic
(Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols.
Enable
rx_enh_blk_lock port
On / Off
Enables the rx_enh_blk_lock port. When you enable the block
synchronizer, this signal is asserted to indicate that the block
delineation has been achieved.
Table 28. Gearbox Parameters
Parameter Range Description
Enable TX data bitslip On / Off When you turn on this option, the TX gearbox operates in bitslip
mode. The tx_enh_bitslip port controls number of bits which TX
parallel data slips before going to the PMA.
Enable TX data polarity
inversion
On / Off When you turn on this option, the polarity of TX data is inverted.
This allows you to correct incorrect placement and routing on the
PCB.
Enable RX data bitslip On / Off When you turn on this option, the Enhanced PCS RX block
synchronizer operates in bitslip mode. When enabled, the
rx_bitslip port is asserted on the rising edge to ensure that RX
parallel data from the PMA slips by one bit before passing to the
PCS.
Enable RX data
polarity inversion
On / Off When you turn on this option, the polarity of the RX data is
inverted. This allows you to correct incorrect placement and
routing on the PCB.
Enable tx_enh_bitslip
port
On / Off Enables the tx_enh_bitslip port. When TX bit slip is enabled,
this signal controls the number of bits which TX parallel data slips
before going to the PMA.
Enable rx_bitslip port On / Off Enables the rx_bitslip port. When RX bit slip is enabled, the
rx_bitslip signal is asserted on the rising edge to ensure that
RX parallel data from the PMA slips by one bit before passing to
the PCS. This port is shared between Standard PCS and Enhanced
PCS.
Note: If a design is slipping more bits than the PCS/PMA width, the Enhanced RX PCS FIFO
could overflow. To clear the overflow, assert rx_digitalreset.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
61

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex