Table 61. Bit Encodings for Basic Double Width Mode
For basic double width mode, the total word length is 66-bit with 128-bit data and 4-bit synchronous header.
Name Bit Functionality Description
tx_control
[1:0] Synchronous header The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[8:2] Unused
[10:9] Synchronous header The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[17:11] Unused
Table 62. Bit Encodings for Basic Mode
In this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.
Name Bit Functionality Description
tx_control
[1:0] Synchronous header The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
[2] Inversion control A logic low indicates that built-in disparity
generator block in the Enhanced PCS maintains
the running disparity.
Enhanced PCS RX Control Port Bit Encodings
Table 63. Bit Encodings for Interlaken
Name Bit Functionality Description
rx_control
[1:0] Synchronous header The value 2'b01 indicates a data
word. The value 2'b10 indicates a
control word.
[2] Inversion control A logic low indicates that the built-
in disparity generator block in the
Enhanced PCS maintains the
Interlaken running disparity. In the
current implementation, this bit is
always tied logic low (1'b0).
[3] Payload word location A logic high (1'b1) indicates the
payload word location in a
metaframe.
[4] Synchronization word location A logic high (1'b1) indicates the
synchronization word location in a
metaframe.
[5] Scrambler state word location A logic high (1'b1) indicates the
scrambler word location in a
metaframe.
[6] SKIP word location A logic high (1'b1) indicates the
SKIP word location in a metaframe.
[7] Diagnostic word location A logic high (1'b1) indicates the
diagnostic word location in a
metaframe.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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