Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1026
Dec 10, 2015
Figure 16-6. Format of IICA Control Register 00 (IICCTL00) (3/4)
STT0
Note
Start condition trigger
0 Do not generate a start condition.
1 When bus is released (in standby state, when IICBSY0 = 0):
If this bit is set (1), a start condition is generated (startup as the master).
When a third party is communicating:
 When communication reservation function is enabled (IICRSV0 = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
 When communication reservation function is disabled (IICRSV0 = 1)
Even if this bit is set (1), the STT0 bit is cleared and the STT0 clear flag (STCF0) is set (1). No start
condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
 For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the
ACKE0 bit has been cleared to 0 and slave has been notified of final reception.
 For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
during the wait period that follows output of the ninth clock.
 Cannot be set to 1 at the same time as stop condition trigger (SPT0).
 Once STT0 is set (1), setting it again (1) before the clear condition is met is not allowed.
Condition for clearing (STT0 = 0) Condition for setting (STT0 = 1)
 Cleared by setting the STT0 bit to 1 while
communication reservation is prohibited.
 Cleared by loss in arbitration
 Cleared after start condition is generated by master
device
 Cleared by LREL0 = 1 (exit from communications)
 When IICE0 = 0 (operation stop)
 Reset
 Set by instruction
Note The signal of this bit is invalid while IICE0 is 0.
Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
2. IICRSV0: Bit 0 of IICA flag register 0 (IICF0)
STCF0: Bit 7 of IICA flag register 0 (IICF0)

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit