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Renesas RL78 Series User Manual

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1056
Dec 10, 2015
Figure 16-28. Communication Reservation Protocol
Notes 1. The wait time is calculated as follows.
(IICWL0 setting value + IICWH0 setting value + 4) / f
MCK + tF 2
2. The communication reservation operation executes a write to the IICA shift register 0 (IICA0) when a stop
condition interrupt request occurs.
Remark STT0: Bit 1 of IICA control register 00 (IICCTL00)
MSTS0: Bit 7 of IICA status register 0 (IICS0)
IICA0: IICA shift register 0
IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
tF: SDAA0 and SCLA0 signal falling times
f
MCK: Frequency of the IICA operation clock
DI
SET1 STT0
Define communication
reservation
Wait
MSTS0 = 0?
(Communication reservation)
Note 2
Yes
No
(Generate start condition)
Cancel communication
reservation
MOV IICA0, #××H
EI
Sets STT0 flag (communication reservation)
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM)
Secures wait time
Note 1
by software.
Confirmation of communication reservation
Clear user flag
IICA0 write operation

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Renesas RL78 Series Specifications

General IconGeneral
CoreRL78
CPU Clock SpeedUp to 32 MHz
Flash MemoryUp to 512 KB
RAMUp to 32 KB
Operating Voltage1.6 V to 5.5 V
Low Power ModesHALT, STOP, SNOOZE
CPU Architecture16-bit
Temperature Range-40°C to +85°C
PackageLQFP
Timers16-bit timers
Communication InterfacesUART, I2C, LIN
A/D Converter12-bit

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