EasyManuals Logo

Renesas RL78 Series User Manual

Renesas RL78 Series
1879 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #1089 background imageLoading...
Page #1089 background image
RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1057
Dec 10, 2015
(2) When communication reservation function is disabled (bit 0 (IICRSV0) of IICA flag register 0 (IICF0) = 1)
When bit 1 (STT0) of IICA control register 00 (IICCTL00) is set to 1 when the bus is not used in a communication
during bus communication, this request is rejected and a start condition is not generated. The following two statuses
are included in the status where bus is not used.
When arbitration results in neither master nor slave operation
When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released
by setting bit 6 (LREL0) of the IICCTL00 register to 1 and saving communication)
To confirm whether the start condition was generated or request was rejected, check STCF0 (bit 7 of the IICF0
register). It takes up to 5 cycles of the operation clock (f
MCK) until the STCF0 bit is set to 1 after setting STT0 = 1.
Therefore, secure the time by software.

Table of Contents

Other manuals for Renesas RL78 Series

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Renesas RL78 Series and is the answer not in the manual?

Renesas RL78 Series Specifications

General IconGeneral
CoreRL78
CPU Clock SpeedUp to 32 MHz
Flash MemoryUp to 512 KB
RAMUp to 32 KB
Operating Voltage1.6 V to 5.5 V
Low Power ModesHALT, STOP, SNOOZE
CPU Architecture16-bit
Temperature Range-40°C to +85°C
PackageLQFP
Timers16-bit timers
Communication InterfacesUART, I2C, LIN
A/D Converter12-bit

Related product manuals