Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1062
Dec 10, 2015
Figure 16-30. Master Operation in Multi-Master System (2/3)
Note The wait time is calculated as follows.
(IICWL0 setting value + IICWH0 setting value + 4) / f
MCK + tF  2
Remark IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F: SDAA0 and SCLA0 signal falling times
f
MCK: Frequency of the IICA operation clock
STT0 = 1
Wait
Slave operation
Yes
MSTS0 = 1?
EXC0 = 1 or COI0 =1?
Prepares for starting communication
(generates a start condition).
Secure wait time
Note
by software.
Waits for bus release
(communication being reserved).
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
No
INTIICA0
interrupt occurs?
Yes
Yes
No
No
A
C
STT0 = 1
Wait
Slave operation
Yes
IICBSY0 = 0?
EXC0 = 1 or COI0 =1?
Prepares for starting communication
(generates a start condition).
Wait for five cycles of the operation clock (f
MCK )
Disables reserving communication.
Enables reserving communication.
Waits for bus release
Detects a stop condition.
No
No
INTIICA0
interrupt occurs?
Yes
Yes
No
Yes
STCF0 = 0?
No
B
D
C
D
Communication processing Communication processing

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit