Name: Renesas RL78 Series
Brand: Renesas
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RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA

R01UH0368EJ0210 Rev.2.10 1097

Dec 10, 2015

The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 18-33 are explained below.

<1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 =1 changes

SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0). When the start condition is

subsequently detected, the master device enters the master device communication status (MSTS0 = 1). The

master device is ready to communicate once the bus clock line goes low (SCLA0 = 0) after the hold time has

elapsed.

<2> The master device writes the address + R (reception) to the IICA shift register 0 (IICA0) and transmits the

slave address.

<3> In the slave device if the address received matches the address (SVA0 value) of a slave device

Note

, that slave

device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0

= 1) at the rising edge of the 9th clock.

<4> The master device issues an interrupt (INTIICA0: end of address transmission) at the falling edge of the 9th

clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLA0 =

0) and issues an interrupt (INTIICA0: address match)

Note

<5> The timing at which the master device sets the wait status changes to the 8th clock (WTIM0 = 0).

<6> The slave device writes the data to transmit to the IICA0 register and releases the wait status that it set by

the slave device.

<7> The master device releases the wait status (WREL0 = 1) and starts transferring data from the slave device

to the master device.

Note If the transmitted address does not match the address of the slave device, the slave device does not return

an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0

interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICA0

interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.

Remark <1> to <19> in Figure 16-33 represent the entire procedure for communicating data using the I

C bus.

Figure 16-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 16-33 (2)

Address ~ data ~ data shows the processing from <3> to <12>, and Figure 16-33 (3) Data ~ data ~ stop

condition shows the processing from <8> to <19>.

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