Renesas RL78 Series - Page 1176

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1144
Dec 10, 2015
(8) LIN Self-Test Control Register (LSTCn)
Address: F06C4H
7 6 5 4 3 2 1 0
LSTM
Value after reset:
0 0 0 0 0 0 0 0
Bit Symbol Bit Name Function R/W
7 to 0 Writing A7H, 58H, and 01H successively to these bits places the module into LIN self-test mode. R/W
0 LSTM LIN Self-Test Mode 0: The module is not in LIN self-test mode
1: The module is in LIN self-test mode.
R/W
The LSTCn register cancels protection of LIN self-test mode.
Set the LSTCn register when the OMM0 bit in the LMSTn register is 0 (LIN reset mode).
Writing A7H, 58H, and 01H successively to the LSTCn register places the module into LIN self-test mode.
When successive writing is completed thus placing LIN self-test mode to be entered, the LSTM bit is set to 1.
Do not write any other value during successive writing.
For making transition to LIN self-test mode, refer to 17.6 LIN Self-Test Mode.
Reading bits 6 to 1 returns 000000b, and reading bit 7 returns the undefined value.
LSTM bit (LIN self-test mode bit)
When transition to LIN self-test mode is completed, the LSTM bit is set to 1.
For leaving LIN self-test mode, refer to 17.6 LIN Self-Test Mode.
Writing 1 to this bit does not affect the value of the LSTCn register if it is not a part of successive writing of A7H, 58H, and
01H.