Renesas RL78 Series - Page 1178

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1146
Dec 10, 2015
(10) LIN Break Field Configuration Register/UART Configuration Register (LBFCn)
Address: F06C9H
7 6 5 4 3 2 1 0
— — — — — — — BLT
Value after reset:
0 0 0 0 0 0 0 0
Bit Symbol Bit Name Function R/W
0 BLT Reception Break (Low) Width Select 0: Reception break (low width) of 9.5/10 or more Tbits is
detected.
1: Reception break (low width) of 10.5/11 or more Tbits is
detected.
R/W
6 to 1 — Reserved These bits are always read as 0. The write value should
always be 0.
R/W
7 — Reserved This bit is always read as 0. The write value should always
be 0.
R/W
Set the LBFCn register when the OMM0 bit in the LMSTn register is 0 (LIN reset mode).
BLT bit (reception break (low) width select bit)
The BLT bit sets the critical low width of the received data to be determined as break.
In LIN slave mode with auto baud rate (the LMD bits in the LMDn register are 10b):
With 0 set, the low width of 10 or more Tbits is detected.
With 1 set, the low width of 11 or more Tbits is detected.
In LIN slave mode with fixed baud rate (the LMD bits in the LMDn register are 11b):
With 0 set, the low width of 9.5 or more Tbits is detected.
With 1 set, the low width of 10.5 or more Tbits is detected.