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Renesas RL78 Series - Page 1191

Renesas RL78 Series
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RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1159
Dec 10, 2015
CSER flag (checksum error flag)
Only 0 can be written to the CSER flag; when 1 is written, the bit retains the value that has been retained before 1 is written.
The CSER flag is set to 1 upon checksum error detection. To clear the bit to 0, write 0 to the bit.
IPER flag (ID parity error flag)
Only 0 can be written to the IPER flag; when 1 is written, the bit retains the value that has been retained before 1 is written.
The IPER flag is set to 1 upon ID parity error detection if the IPERE bit in the LEDEn register is 1 (ID parity error detection
is enabled). To clear the bit to 0, write 0 to the bit.
RPER flag (response preparation error flag)
Only 0 can be written to the RPER flag; when 1 is written, the bit retains the value that has been retained before 1 is written.
The RPER flag is set to 1 upon response preparation error detection. To clear the bit to 0, write 0 to the bit.

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