Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1222
Dec 10, 2015
The aforementioned timeout time is a time greater than the TFRAME_MAX of LIN Specification Package
Revision 1.3 on classic selection, or the TFRAME_MAX of LIN Specification Package Revision 2.x on
enhanced selection.
[Response timeout]
Timeout time = (number of data bytes + 1) × 14 [Tbit]
4. Only indication in the SFER flag can be enabled or disabled; error detection cannot be enabled or disabled.
5. Checksum determination is performed after response frame reception is completed. If the result is determined
as an error, the successful reception flag is not set to 1.
Caution The error status is cleared when cleared by software or after transition to LIN reset mode.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit