RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1268
Dec 10, 2015
Table 18-3. List of CAN Module Registers (6/22)
Address Special Function Register (SFR) Name Symbol R/W Access Size After
Reset
1 bit 8 bits 16 bits
F03DAH CAN receive rule entry register 4CH
Note 1
GAFLPH4L GAFLPH4 R/W — √ √ 0000H
F03DBH GAFLPH4H — √
F03DAH CAN receive buffer register 3CH
Note 2
RMDF13L RMDF13 R — √ √ 0000H
F03DBH RMDF13H — √
F03DCH CAN receive rule entry register 5AL
Note 1
GAFLIDL5L GAFLIDL5 R/W — √ √ 0000H
F03DDH GAFLIDL5H — √
F03DCH CAN receive buffer register 3DL
Note 2
RMDF23L RMDF23 R — √ √ 0000H
F03DDH RMDF23H — √
F03DEH CAN receive rule entry register 5AH
Note 1
GAFLIDH5L GAFLIDH5 R/W — √ √ 0000H
F03DFH GAFLIDH5H — √
F03DEH CAN receive buffer register 3DH
Note 2
RMDF33L RMDF33 R — √ √ 0000H
F03DFH RMDF33H — √
F03E0H CAN receive rule entry register 5BL
Note 1
GAFLML5L GAFLML5 R/W — √ √ 0000H
F03E1H GAFLML5H — √
F03E0H CAN receive buffer register 4AL
Note 2
RMIDL4L RMIDL4 R — √ √ 0000H
F03E1H RMIDL4H — √
F03E2H CAN receive rule entry register 5BH
Note 1
GAFLMH5L GAFLMH5 R/W — √ √ 0000H
F03E3H GAFLMH5H — √
F03E2H CAN receive buffer register 4AH
Note 2
RMIDH4L RMIDH4 R — √ √ 0000H
F03E3H RMIDH4H — √
F03E4H CAN receive rule entry register 5CL
Note 1
GAFLPL5L GAFLPL5 R/W — √ √ 0000H
F03E5H GAFLPL5H — √
F03E4H CAN receive buffer register 4BL
Note 2
RMTS4L RMTS4 R — √ √ 0000H
F03E5H RMTS4H — √
F03E6H CAN receive rule entry register 5CH
Note 1
GAFLPH5L GAFLPH5 R/W — √ √ 0000H
F03E7H GAFLPH5H — √
F03E6H CAN receive buffer register 4BH
Note 2
RMPTR4L RMPTR4 R — √ √ 0000H
F03E7H RMPTR4H — √
F03E8H CAN receive rule entry register 6AL
Note 1
GAFLIDL6L GAFLIDL6 R/W — √ √ 0000H
F03E9H GAFLIDL6H — √
F03E8H CAN receive buffer register 4CL
Note 2
RMDF04L RMDF04 R — √ √ 0000H
F03E9H RMDF04H — √
F03EAH CAN receive rule entry register 6AH
Note 1
GAFLIDH6L GAFLIDH6 R/W — √ √ 0000H
F03EBH GAFLIDH6H — √
F03EAH CAN receive buffer register 4CH
Note 2
RMDF14L RMDF14 R — √ √ 0000H
F03EBH RMDF14H — √
F03ECH CAN receive rule entry register 6BL
Note 1
GAFLML6L GAFLML6 R/W — √ √ 0000H
F03EDH GAFLML6H — √
F03ECH CAN receive buffer register 4DL
Note 2
RMDF24L RMDF24 R — √ √ 0000H
F03EDH RMDF24H — √
F03EEH CAN receive rule entry register 6BH
Note 1
GAFLMH6L GAFLMH6 R/W — √ √ 0000H
F03EFH GAFLMH6H — √
Notes 1. These registers are allocated to RAM window 0 for the CAN module (receive rules and CAN RAM test
register). When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.
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