RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1267
Dec 10, 2015
Table 18-3. List of CAN Module Registers (5/22)
Address Special Function Register (SFR) Name Symbol R/W Access Size After
Reset
1 bit 8 bits 16 bits
F03C4H CAN receive buffer register 2BL
Note 2
RMTS2L RMTS2 R — √ √ 0000H
F03C5H RMTS2H — √
F03C6H CAN receive rule entry register 3AH
Note 1
GAFLIDH3L GAFLIDH3 R/W — √ √ 0000H
F03C7H GAFLIDH3H — √
F03C6H CAN receive buffer register 2BH
Note 2
RMPTR2L RMPTR2 R — √ √ 0000H
F03C7H RMPTR2H — √
F03C8H CAN receive rule entry register 3BL
Note 1
GAFLML3L GAFLML3 R/W — √ √ 0000H
F03C9H GAFLML3H — √
F03C8H CAN receive buffer register 2CL
Note 2
RMDF02L RMDF02 R — √ √ 0000H
F03C9H RMDF02H — √
F03CAH CAN receive rule entry register 3BH
Note 1
GAFLMH3L GAFLMH3 R/W — √ √ 0000H
F03CBH GAFLMH3H — √
F03CAH CAN receive buffer register 2CH
Note 2
RMDF12L RMDF12 R — √ √ 0000H
F03CBH RMDF12H — √
F03CCH CAN receive rule entry register 3CL
Note 1
GAFLPL3L GAFLPL3 R/W — √ √ 0000H
F03CDH GAFLPL3H — √
F03CCH CAN receive buffer register 2DL
Note 2
RMDF22L RMDF22 R — √ √ 0000H
F03CDH RMDF22H — √
F03CEH CAN receive rule entry register 3CH
Note 1
GAFLPH3L GAFLPH3 R/W — √ √ 0000H
F03CFH GAFLPH3H — √
F03CEH CAN receive buffer register 2DH
Note 2
RMDF32L RMDF32 R — √ √ 0000H
F03CFH RMDF32H — √
F03D0H CAN receive rule entry register 4AL
Note 1
GAFLIDL4L GAFLIDL4 R/W — √ √ 0000H
F03D1H GAFLIDL4H — √
F03D0H CAN receive buffer register 3AL
Note 2
RMIDL3L RMIDL3 R — √ √ 0000H
F03D1H RMIDL3H — √
F03D2H CAN receive rule entry register 4AH
Note 1
GAFLIDH4L GAFLIDH4 R/W — √ √ 0000H
F03D3H GAFLIDH4H — √
F03D2H CAN receive buffer register 3AH
Note 2
RMIDH3L RMIDH3 R — √ √ 0000H
F03D3H RMIDH3H — √
F03D4H CAN receive rule entry register 4BL
Note 1
GAFLML4L GAFLML4 R/W — √ √ 0000H
F03D5H GAFLML4H — √
F03D4H CAN receive buffer register 3BL
Note 2
RMTS3L RMTS3 R — √ √ 0000H
F03D5H RMTS3H — √
F03D6H CAN receive rule entry register 4BH
Note 1
GAFLMH4L GAFLMH4 R/W — √ √ 0000H
F03D7H GAFLMH4H — √
F03D6H CAN receive buffer register 3BH
Note 2
RMPTR3L RMPTR3 R — √ √ 0000H
F03D7H RMPTR3H — √
F03D8H CAN receive rule entry register 4CL
Note 1
GAFLPL4L GAFLPL4 R/W — √ √ 0000H
F03D9H GAFLPL4H — √
F03D8H CAN receive buffer register 3CL
Note 2
RMDF03L RMDF03 R — √ √ 0000H
F03D9H RMDF03H — √
Notes 1. These registers are allocated to RAM window 0 for the CAN module (receive rules and CAN RAM test
register). When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.
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