Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 24 RESET FUNCTION
R01UH0368EJ0210 Rev.2.10 1543
Dec 10, 2015
Figure 24-2. Timing of Reset by RESET Input
Figure 24-3. Timing of Reset by Watchdog Timer Overflow, Execution of Illegal Instruction, Clock Monitor, or
Illegal-Memory Access
(Notes, Caution, and Remark are listed on the next page.)
Delay
Hi-Z
Normal operationCPU status
Normal operation
(high-speed on-chip oscillator clock)
RESET
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Note 1
High-speed system clock
(when X1 oscillation is selected)
High-speed on-chip
oscillator clock
Starting X1 oscillation is specified by software.
Reset processing
Wait for oscillation
accuracy stabilization
Reset period
Note 2
Normal operation
Reset period
(oscillation stop)
CPU status
Watchdog timer overflow/
execution of illegal instruction/
clock monitor/
illegal memory access
Internal reset signal
Hi-Z
Note 1
High-speed system clock
(when X1 oscillation is selected)
High-speed on-chip
oscillator clock
Starting X1 oscillation is specified by software.
Normal operation
(high-speed on-chip oscillator clock)
Wait for oscillation
accuracy stabilization
Reset processing
Port pin
(except P130)
Port pin
(P130)
0.0511 ms (typ.)
0.0701 ms (max.)

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit