RL78/F13, F14 CHAPTER 24 RESET FUNCTION
R01UH0368EJ0210 Rev.2.10 1544
Dec 10, 2015
Figure 24-4. Timing of Reset in STOP Mode by RESET Input
Notes 1. When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummy-
output as a reset signal to an external device, because P130 outputs a low level when reset is effected. To
release a reset signal to an external device, set P130 to high-level output by software.
2. Reset processing time when the external reset is released is shown below.
After the first release of POR: 0.672 ms (typ.), 0.832 ms (max.) (when the LVD is in use)
0.399 ms (typ.), 0.519 ms (max.) (when the LVD is off)
After the second release of POR: 0.531 ms (typ.), 0.675 ms (max.) (when the LVD is in use)
0.259 ms (typ.), 0.362 ms (max.) (when the LVD is off)
After power is supplied, a voltage stabilization waiting time of about 0.99 ms (typ.) and up to 2.30 ms (max.)
is required before reset processing starts after release of the external reset.
Remark For the reset timing of the power-on-reset circuit and voltage detector, see CHAPTER 25 POWER-ON-RESET
CIRCUIT and CHAPTER 26 VOLTAGE DETECTOR.
Delay
Normal
operation
CPU status
Reset period
RESET
Internal reset signal
STOP instruction execution
Stop status
(oscillation stop)
High-speed system clock
(when X1 oscillation is selected)
High-speed on-chip
oscillator clock
Hi-Z
Note 1
Starting X1 oscillation is specified by software.
Normal operation
(high-speed on-chip oscillator clock)
Wait for oscillation
accuracy stabilization
Reset processing
Note 2
Port pin
(except P130)
Port pin
(P130)
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