RL78/F13, F14 CHAPTER 27 SAFETY FUNCTIONS
R01UH0368EJ0210 Rev.2.10 1597
Dec 10, 2015
(1) SPM control register (SPMCTRL)
Figure 27-15. Format of SPM Control Register (SPMCTRL)
Address: F00D8H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
SPMCTRL
SPMEN - - - - - - -
SPMEN Stack pointer monitor SFR write enable/disable
0 Stack pointer monitoring disabled.
1 Stack pointer monitoring enabled.
Caution Writing 1 to the SPMEN bit is only valid, and writing 0 after setting SPMEN to 1 is invalid.
(2) SP overflow address setting register (SPOFR)
Figure 27-16. Format of SP Overflow Address Setting Register (SPOFR)
Address: F00DAH After reset: FFFEH R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPOFR - - - - - - - - - - - - - - - -
- Stack pointer overflow address setting
0 Stack pointer overflow address
1
Cautions 1. The lowest bit is fixed to 0.
2. If the values of bits 15 to 1 in stack pointer are greater than the specified values of bits 15
to 1 in SPOFR, an interrupt signal (INTSPM) is generated.
Stack pointer > SPOFR: INTSPM interrupt signal is generated.
3. When SPMEN = 1, writing to SPOFR is invalid.
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