Renesas RL78 Series

RL78/F13, F14 CHAPTER 36 ELECTRICAL SPECIFICATIONS (GRADE Y)
R01UH0368EJ0210 Rev.2.10 1819
Dec 10, 2015
(11) During communication at different potential (3-V supply system) (simplified I
2
C mode)
(SDAr: TTL input buffer mode or N-ch open-drain output (EV
DD0 tolerance) mode, SCLr: N-ch open-drain
output (EV
DD0 tolerance) mode)
(TA = -40 to +150C, 4.0 V  EVDD0 = EVDD1 = VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
SCLr clock frequency fSCL 2.7 V  Vb  4.0 V,
C
b = 100 pF, Rb = 1.4 kΩ
400
Note
kHz
Hold time when SCLr = ”L” tLOW 2.7 V  Vb  4.0 V,
C
b = 100 pF, Rb = 1.4 kΩ
1200 ns
Hold time when SCLr = ”H” tHIGH 2.7 V  Vb  4.0 V,
C
b = 100 pF, Rb = 1.4 kΩ
600 ns
Data setup time (reception) tSU:DAT 2.7 V  Vb  4.0 V,
C
b = 100 pF, Rb = 1.4 kΩ
135 + 1/f
MCK ns
Data hold time (transmission) tHD:DAT 2.7 V  Vb  4.0 V,
C
b = 100 pF, Rb = 1.4 kΩ
0 140 ns
Note fSCL  fMCK/4 must also be satisfied.