Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 36 ELECTRICAL SPECIFICATIONS (GRADE Y)
R01UH0368EJ0210 Rev.2.10 1820
Dec 10, 2015
Simplified I
2
C mode connection diagram (during communication at different potential)
Simplified I
2
C mode serial transfer timing (during communication at different potential)
Caution Select the TTL input buffer and the N-ch open-drain output mode for the SDAr pin and N-ch open-drain
output mode for the SCLr pin.
Remarks 1. R
b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load
capacitance, V
b [V]: Communication line voltage
2. f
MCK: Serial array unit operation clock frequency
SDAr
SCLr
SDA
SCL
User's device
Vb
Rb
Vb
Rb
RL78
microcontroller
SDAr
t
LOW
t HIGH
t HD : DAT
SCLr
t SU : DAT
1/f SCL

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit