Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 37 PACKAGE DRAWING
R01UH0368EJ0210 Rev.2.10 1836
Dec 10, 2015
37.4.2 48-pin VQFN
JEITA Package code RENESAS code Previous code MASS(TYP.)[g]
P-HVQFN48-7x7-0.50 PVQN0048KG-A P48K9-50A-BAJ 0.13
D
A
Lp
H
0.20
5.40
0.40
6.75
6.75
5.40
Referance
Symbol
Min
Nom Max
Dimension in Millimeters
0.30
0.30
0.50
b
0.20
x
A
0.90
y
0.05
H
7.00
6.95
7.05
DETAIL OF A PART
S
y
e
Lp
SxbAB
M
A
D
E
36
37
24
25
12
13
1
48
H
S
EXPOSED DIE PAD
D
E
B
A
0.00
0.25
H
INDEX MARK
Z
Z
1
12
13
24
25
36
37
48
e
Z
Z
c
D
E
1
D
E
D
E
2
2
2
E
0.50
0.10
7.00
6.95
7.05
0.75
0.75
0.19
0.21
A
A
1
c
2
E
D
D
E
2
2
Dimple

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit