Renesas RL78 Series

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RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR

R01UH0368EJ0210 Rev.2.10 363

Dec 10, 2015

(2) PLL clock

This clock oscillates the clock whose f

PLL is 24 MHz, 32 MHz, or 64 MHz by oscillating the main system clock at 4

MHz or 8 MHz and multiplying by 3, 4, 6, or 8 times. When setting f

PLL to 64 MHz or 48 MHz, the division of fCLK

should be set to 32 MHz or 24 MHz by the MDIV2 to MDIV0 bits in the f

MP clock division register (MDIV). Oscillation

can be stopped by setting the PLLON bit (bit 0 of the PLLCTL register). Before entering STOP mode, the PLLON

bit should be cleared to 0 (Stops PLL operation).

Remarks 1. The PLL input clock frequency can be set to 4 MHz or 8 MHz. When setting the high-speed on-chip oscillator

clock as the PLL input clock, the on-chip oscillator clock can be set to 4 MHz or 8 MHz depending on the

setting of bits 4 to 0 (FRQSEL4 to FRQSEL0) of the user option byte (000C2H/020C2H). For details of the

user option byte, see CHAPTER 29 OPTION BYTE.

2. Set the multiplier of the PLL clock by bits 1 (PLLMUL) and 4 (PLLDIV0) in the PLL control register (PLLCTL).

(3) Subsystem clock

 XT1 clock oscillator

This circuit oscillates a clock of f

XT = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2. Oscillation

can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)).

An external subsystem clock (f

EXS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. An external

subsystem clock input can be disabled by setting the XTSTOP bit (bit 6 of the clock operation status control register

(CSC)).

As the subsystem clock, an XT1 clock or external subsystem clock can be selected by setting of the OSCSELS bit

(bit 4 of the clock operation mode control register (CMC)), the EXCLKS bit (bit 5 of the clock operation mode control

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