Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 364
Dec 10, 2015
(4) Low-speed on-chip oscillator (Low-speed OCO)
This circuit oscillates a clock of f
IL = 15 kHz (TYP.).
The low-speed on-chip oscillator clock can be used as the CPU/peripheral hardware clock.
Only the following hardware circuits operate by the low-speed on-chip oscillator clock.
 Clock monitor (f
IL)
 Timer RJ (f
IL and fSL)
 Timer RD (f
SL)
 Clock output/buzzer output control circuit (fSL)
This circuit operates when at least bit 4 in the operation speed mode control register (OSMC) or bit 6 in the clock
select register (SELLOSC) is 1. When stopping the oscillation of the low-speed on-chip oscillator, set the
WUTMMCK0 and SELLOSC bits to 0.
As the main/PLL select clock (f
MP), a main system clock (fMAIN) or PLL clock (fPLL) can be selected by setting of the
SELPLL bit (bit 2 of the PLL control register (PLLCTL)).
As the subsystem/low-speed on-chip oscillator select clock (f
SL), a subsystem clock (fSUB) or low-speed on-chip
oscillator (f
IL) can be selected by setting of the CKSEL bit (bit 0 of the clock select register (CKSEL)).
Remark fX: X1 clock oscillation frequency
f
IH: High-speed on-chip oscillator clock frequency (64 MHz max.)
Note
f
EX: External main system clock frequency
f
XT: XT1 clock oscillation frequency
fEXS: External subsystem clock frequency
f
IL: Low-speed on-chip oscillator clock frequency
f
SL: Subsystem/low-speed on-chip oscillator select clock frequency
fPLL: PLL clock frequency (64 MHz max.) Notes 2 and 3
f
MP: Main/PLL select clock frequency (64 MHz max.)
Notes 1. f
IH is controlled by hardware so that the MDIV register is set to 01H (fMP = two frequency division) when fIH is
set to 64 MHz or 48 MHz after a reset release. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to
f
IH.
2. When setting f
PLL to 64 MHz or 48 MHz, the division of fMP should be set within the range of 1 MHz to 32 MHz
(or 1 MHz to 24 MHz for grade-K and grade-Y products) by the MDIV2 to MDIV0 bits in the f
MP clock division
register (MDIV). When supplying 64 MHz or 48 MHz to timer RD, set f
CLK to fPLL.
3. When supplying 64 MHz or 48 MHz to timer RD, set the MDIV register to 01H (f
MP/2 is selected).

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit