Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 500
Dec 10, 2015
Figure 6-52. Example of Basic Timing of Operation as Frequency Divider (MDmn0 = 1)
Remark TS00: Bit n of timer channel start register m (TSm)
TE00: Bit n of timer channel enable status register m (TEm)
TI00: TI00 pin input signal
TCR00: Timer count register 00 (TCR00)
TDR00: Timer data register 00 (TDR00)
TO00: TO00 pin output signal
TS00
TE00
TI00
TDR00
TCR00
TO00
INTTM00
0002H
Divided
by 6
0001H
0
0000H
1
2
0
1
2
0
1
0
1
0
1
0
1
0
1
2
Divided
by 4

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit