RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 501
Dec 10, 2015
Figure 6-53. Example of Set Contents of Registers During Operation as Frequency Divider
(a) Timer mode register 00 (TMR00)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR00
CKS0n1
1/0
CKS0n0
1/0
0
CCS00
1
MAS
TER00
0
STS002
0
STS001
0
STS000
0
CIS001
1/0
CIS000
1/0
0
0
MD003
0
MD002
1
MD001
1
MD000
1/0
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTM00 nor inverts
timer output when counting is started.
1: Generates INTTM00 and inverts timer
output when counting is started.
Selection of TI00 pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Independent channel operation function.
Count clock selection
1: Selects the TI00 pin input valid edge.
Operation clock (f
MCK) selection
00B: Selects CKm0 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
11B: Selects CKm3 as operation clock of channel n.
(b) Timer output register m (TOm)
Bit n
TOm
TO00
1/0
0: Outputs 0 from TO00.
1: Outputs 1 from TO00.
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOE00
1/0
0: Stops the TO00 output operation by counting operation.
1: Enables the TO00 output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit n
TOLm
TOL00
0
0: Cleared to 0 when TOM00 = 0 (master channel output mode)
(e) Timer output mode register m (TOMm)
Bit n
TOMm
TOM00
0
0: Sets master channel output mode.
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