RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 522
Dec 10, 2015
Figure 6-70. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel)
(a) Timer mode register mp (TMRmp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMRmp
CKSmp1
1/0
CKSmp0
0
0
CCSmp
0
M/S
Note
0
STSmp2
1
STSmp1
0
STSmp0
0
CISmp1
0
CISmp0
0
0
0
MDmp3
1
MDmp2
0
MDmp1
0
MDmp0
0
Operation mode of channel p
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TImp pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTMmn of master channel.
Setting of MASTERmp, MASTERmq bits (channels 2, 4, 6)
0: Slave channel.
Setting of SPLITmp, SPLITmq bits (channels 1, 3)
0: 16-bit timer mode.
Count clock selection
0: Selects operation clock (f
MCK).
Operation clock (f
MCK) selection
00B: Selects CKm0 as operation clock of channel p.
01B: Selects CKm2 as operation clock of channel p.
10B: Selects CKm1 as operation clock of channel p.
11B: Selects CKm3 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register m (TOm)
Bit p
TOm
TOmp
1/0
0: Outputs 0 from TOmp.
1: Outputs 1 from TOmp.
(c) Timer output enable register m (TOEm)
Bit p
TOEm
TOEmp
1/0
0: Stops the TOmp output operation by counting operation.
1: Enables the TOmp output operation by counting operation.
(d) Timer output level register m (TOLm)
Bit p
TOLm
TOLmp
1/0
0: Positive logic output (active-high)
1: Negative logic output (active-low)
(e) Timer output mode register m (TOMm)
Bit p
TOMm
TOMmp
1
1: Sets the slave channel output mode.
Note TMRm2, TMRm4, TMRm6: MASTERmp bit
TMRm1, TMRm3: SPLITmp bit
TMRm5, TMRm7: Fixed to 0
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