Renesas RL78 Series - Page 613

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 581
Dec 10, 2015
Figure 8-12. Format of Timer RD Output Control Register (TRDOCR) [PWM Function]
Address: F0269H After Reset: 00H
Note 1
Symbol 7 6 5 4 3 2 1 0
TRDOCR TOD1
TOC1 TOB1 TOA1 TOD0
TOC0 TOB0 TOA0
TOD1
TRDIOD1 initial output level select
Note 2
R/W
0 Initial output is not active level R/W
1 Initial output is active level
TOC1
TRDIOC1 initial output level select
Note 2
R/W
0 Initial output is not active level R/W
1 Initial output is active level
TOB1
TRDIOB1 initial output level select
Note 2
R/W
0 Initial output is not active level R/W
1 Initial output is active level
TOA1 TRDIOA1 initial output level select R/W
Set to 0. R/W
TOD0
TRDIOD0 initial output level select
Note 2
R/W
0 Initial output is not active level R/W
1 Initial output is active level
TOC0
TRDIOC0 initial output level select
Note 2
R/W
0 Initial output is not active level R/W
1 Initial output is active level
Enabled in reset synchronous and complementary PWM modes.
TOB0
TRDIOB0 initial output level select
Note 2
R/W
0 Initial output is not active level R/W
1 Initial output is active level
TOA0 TRDIOA0 initial output level select R/W
Set to 0. R/W
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN
= 1 before reading.
2. If the pin function is set for waveform output, the initial output level is output when the TRDOCR register
is set.