Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 608
Dec 10, 2015
Table 8-7. TRDGRji Register Functions in Complementary PWM Mode
Register Setting Register Function PWM
Output Pin
TRDGRA0 — General register. Set the PWM period at initialization.
Setting range:  Value set in TRD0 register
 FFFFh - value set in TRD0 register
Do not write to this register when bits TSTART0 and TSTART1
in the TRDSTR register are set to 1 (count starts).
(TRDIOC0,
output
inverted
every half
period)
TRDGRB0 — General register. Set the changing point of PWM1 output at initialization.
Setting range:  Value set in TRD0 register
 Value set in TRDGRA0 register - value set in TRD0 register
Do not write to this register when bits TSTART0 and TSTART1
in the TRDSTR register are set to 1 (count starts).
TRDIOB0
TRDIOD0
TRDGRA1 — General register. Set the changing point of PWM2 output at initialization.
Setting range:  Value set in TRD0 register
 Value set in TRDGRA0 register - value set in TRD0 register
Do not write to this register when bits TSTART0 and TSTART1
in the TRDSTR register are set to 1 (count starts).
TRDIOA1
TRDIOC1
TRDGRB1 — General register. Set the changing point of PWM3 output at initialization.
Setting range:  Value set in TRD0 register
 Value set in TRDGRA0 register - value set in TRD0 register
Do not write to this register when bits TSTART0 and TSTART1
in the TRDSTR register are set to 1 (count starts).
TRDIOB1
TRDIOD1
TRDGRC0 — (Not used in complementary PWM mode.) —
TRDGRD0 TRDBFD0 = 1 Buffer register. Set the changing point of next PWM1 output
(see 8. 3. 1 (2) Buffer Operation).
Setting range:  Value set in TRD0 register
 Value set in TRDGRA0 register - value set in TRD0 register
Set this register to the same value as the TRDGRB0 register for
initialization.
TRDIOB0
TRDIOD0
TRDGRC1 TRDBFC1 = 1 Buffer register. Set the changing point of next PWM2 output
(see 8. 3. 1 (2) Buffer Operation).
Setting range:  Value set in TRD0 register
 Value set in TRDGRA0 register - value set in TRD0 register
Set this register to the same value as the TRDGRA1 register
for initialization.
TRDIOA1
TRDIOC1
TRDGRD1 TRDBFD1 = 1 Buffer register. Set the changing point of next PWM3 output
(see 8. 3. 1 (2) Buffer Operation).
Setting range:  Value set in TRD0 register
 Value set in TRDGRA0 register - value set in TRD0 register
Set this register to the same value as the TRDGRB1 register
for initialization.
TRDIOB1
TRDIOD1
Caution When the setting of bits TCK2 to TCK0 in the TRDCRi register is 000B (f
CLK, fIH, fPLL, fSUB, and fIL) and
the compare value is set to 0000H, a request signal to the data transfer controller (DTC) and the event
link controller (ELC) is generated only once immediately after the count starts. When the compare
value is 0001H or higher, a request signal is generated each time a compare match occurs.
Remark i = 0 or 1, j = A, B, C, or D
TRDBFD0, TRDBFC1, TRDBFD1: Bits in TRDMR register

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit