RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 632
Dec 10, 2015
Figure 8-51 shows an Operation Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin and
TRDGRDi Register is Used for Output Control of TRDIOBi Pin.
Figure 8-51. Operation Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin
and TRDGRDi Register is Used for Output Control of TRDIOBi Pin
m
n
p
Count source
m + 1
n + 1
q
0000H
FFFFH
m - n
p + 1
p - qq + 1
Output inverted by compare match
Output inverted by compare match
Time
Value in TRDi register
TRDIOAi output
IMFA bit in
TRDSRi register
IMFC bit in
TRDSRi register
TRDIOBi output
IMFB bit in
TRDSRi register
IMFD bit in
TRDSRi register
Set to 0 by a program Set to 0 by a program
Set to 0 by a program
Set to 0 by a program
Remark
i = 0 or 1
m: Value set in TRDGRAi register
n: Value set in TRDGRCi register
p: Value set in TRDGRBi register
q: Value set in TRDGRDi register
The above diagram applies under the following conditions :
The CSELi bit in the TRDSTR register is set to 1 (TRDi register is not stopped by compare match).
Bits TRDBFCi and TRDBFDi in the TRDMR register are set to 0 (TRDGRCi and TRDGRDi do not operate as buffers).
Bits EAi and EBi in the TRDOER1 register are set to 0 (TRDIOAi and TRDIOBi output enabled).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001B (TRDi is set to 0000H by compare match with TRDGRAi).
Bits TOAi and TOBi in the TRDOCR register are set to 0 (initial output is low until compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011B (TRDIOAi output inverted at TRDGRAi compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 011B (TRDIOBi output inverted at TRDGRBi compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 0011B (TRDIOAi output inverted at TRDGRCi compare match).
Bits IOD3 to IOD0 in the TRDIORCi register are set to 0011B (TRDIOBi output inverted at TRDGRDi compare match).
Initial output is low
Initial output is low
To Next Page
Loading...
Need help?
General
