Renesas RL78 Series User Manual

Index-3
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 88
3.1 Memory Space .............................................................................................................................. 88
3.1.1 Internal program memory space ..................................................................................................... 114
3.1.2 Mirror area ...................................................................................................................................... 118
3.1.3 Internal data memory space ........................................................................................................... 120
3.1.4 Special function register (SFR) area .............................................................................................. 121
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ...................... 121
3.1.6 Data memory addressing ............................................................................................................... 122
3.2 Processor Registers ................................................................................................................... 140
3.2.1 Control registers ............................................................................................................................. 140
3.2.2 General-purpose registers .............................................................................................................. 143
3.2.3 ES and CS registers ....................................................................................................................... 145
3.2.4 Special function registers (SFRs) ................................................................................................... 146
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ......................... 151
3.3 Instruction Address Addressing ............................................................................................... 184
3.3.1 Relative addressing ........................................................................................................................ 184
3.3.2 Immediate addressing .................................................................................................................... 184
3.3.3 Table indirect addressing ............................................................................................................... 185
3.3.4 Register direct addressing .............................................................................................................. 186
3.4 Addressing for Processing Data Addresses ........................................................................... 187
3.4.1 Implied addressing ......................................................................................................................... 187
3.4.2 Register addressing ....................................................................................................................... 187
3.4.3 Direct addressing ........................................................................................................................... 188
3.4.4 Short direct addressing .................................................................................................................. 189
3.4.5 SFR addressing .............................................................................................................................. 190
3.4.6 Register indirect addressing ........................................................................................................... 191
3.4.7 Based addressing ........................................................................................................................... 192
3.4.8 Based indexed addressing ............................................................................................................. 196
3.4.9 Stack addressing ............................................................................................................................ 197
CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 201
4.1 Port Functions ............................................................................................................................ 201
4.2 Port Configuration ...................................................................................................................... 203
4.2.1 Port 0 .............................................................................................................................................. 204
4.2.2 Port 1 .............................................................................................................................................. 209
4.2.3 Port 3 .............................................................................................................................................. 220
4.2.4 Port 4 .............................................................................................................................................. 226
4.2.5 Port 5 .............................................................................................................................................. 236
4.2.6 Port 6 .............................................................................................................................................. 246
4.2.7 Port 7 .............................................................................................................................................. 256

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit