Intel Arria 10 User Manual

Figure 43. Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with
IEEE 1588v2
RX
FIFO (1)
Byte
Deserializer (4)
8B/10B Decoder
Rate Match FIFO (2)
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX
FIFO (1)
Byte Serializer (3)
8B/10B Encoder
PRBS
Generator
TX Bit Slip
/2
/2
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB) (5)
ATX PLL
CMU PLL
fPLL
tx_coreclkin
rx_coreclkin
rx_clkout or
tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
tx_clkout
tx_clkout
tx_clkout
rx_clkout
PRBS
Verifier
tx_pma_div_clkout
10
625 MHz
125 MHz
10
625 MHz
125 MHz
Notes:
1. This block is set in low latency mode for GbE and register_fifo mode for GbE with IEEE 1588v2.
2. The rate match FIFO of the hard PCS is disabled for GbE with IEEE 1588v2 because it is not able to acheive deterministic latency. It is also disabled for Triple-speed Ethernet (TSE) configurations that require an auto-negotiation sequency.
The insertion/deletion operation could break the auto-negotiation functionality due to the rate matching of different frequency PPM scenarios.The soft rate match FIFO is constructed in the GbE Serial Gigabit Media Independent Interface
(SGMII) IP core.
3. The byte serializer can be enabled or disabled.
4. The byte deserializer can be enabled or disabled.
5. The CGB is in the Native PHY.
8
8
125 MHz
125 MHz
Note: The Native PHY only supports basic PCS functions. The Native PHY does not support
auto-negotiation state machine, collision-detect, and carrier-sense. If required, you
must implement these functions in the FPGA fabric or external circuits.
GbE with IEEE 1588v2
GbE with IEEE 1588v2 provides a standard method to synchronize devices on a
network with submicrosecond precision. To improve performance, the protocol
synchronizes slave clocks to a master clock so that events and time stamps are
synchronized in all devices. The protocol enables heterogeneous systems that include
clocks of various inherent precision, resolution, and stability to synchronize to a
grandmaster clock.
The TX FIFO and RX FIFO are set to register_fifo mode for GbE with IEEE 1588v2.
Related Information
Triple-Speed Ethernet IP Function User Guide.
For more information about the IEEE 1588v2 implementation in GbE PHY and MAC,
and design examples.
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2
The 8B/10B encoder clocks 8-bit data and 1-bit control identifiers from the transmitter
phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded
data is sent to the PMA.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
113

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex