Intel Arria 10 User Manual

Figure 45. Reset Condition
clock
tx_parallel_data
tx_digitalreset
K28.5
K28.5
K28.5
K28.5
xxx
Dx.y
Dx.y
K28.5
K28.5 K28.5Dx.y Dx.y Dx.y
n
n + 1
n + 2
n + 3
n + 4
Automatically transmitted /K28.5/
User transmitted data
User transmitted synchronization sequence
2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2
The word aligner for the GbE and GbE with IEEE 1588v2 protocols is configured in
automatic synchronization state machine mode. The software automatically configures
the synchronization state machine to indicate synchronization when the receiver
receives three consecutive synchronization ordered sets. A synchronization ordered
set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code groups.
The fastest way for the receiver to achieve synchronization is to receive three
continuous {/K28.5/, /Dx.y/} ordered sets.
The GbE PHY IP core signals receiver synchronization status on the rx_syncstatus
port of each channel. A high on the rx_syncstatus port indicates that the lane is
synchronized; a low on the rx_syncstatus port indicates that the lane has fallen out
of synchronization. The receiver loses synchronization when it detects three invalid
code groups separated by less than three valid code groups or when it is reset.
Table 90. Synchronization State Machine Parameter Settings for GbE
Synchronization State Machine Parameter Setting
Number of word alignment patterns to achieve sync 3
Number of invalid data words to lose sync 3
Number of valid data words to decrement error count 3
The following figure shows rx_syncstatus high when three consecutive ordered sets
are sent through rx_parallel_data.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
115

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex