Intel Arria 10 User Manual

Word
Addr
Bit R/W Name Description
5 RO
AN Ability
When set to 1, the transceiver PHY is able to perform Auto
Negotiation. When set to 0, the transceiver PHY i s not able to
perform Auto Negotiation. If your variant includes Auto
Negotiation, this bit is tied to 1. For more information, refer
to 7.1.3 and 7.48.0 of Clause 45 of IEEE 802.3ap-2007.
6 RO
AN Status
When set to 1, link is up. When 0, the link is down. The
current value clears when the register is read. For more
information, refer to 7.1.2 of Clause 45 of IEEE
802.3ap-2007.
7 RO
LP AN Ability
When set to 1, the link partner is able to perform Auto
Negotiation. When 0, the link partner is not able to perform
Auto-Negotiation. For more information, refer to 7.1.0 of
Clause 45 of IEEE 802.3ap-2007.
0x4C2 8 RO
FEC negotiated –
enable FEC from SEQ
When set to 1, PHY is negotiated to perform FEC. When set to
0, PHY is not negotiated to perform FEC.
9 RO
Seq AN Failure
When set to 1, a sequencer Auto Negotiation failure has been
detected. When set to 0, an Auto Negotiation failure has not
been detected.
17:12 RO
KR AN Link
Ready[5:0]
Provides a one-hot encoding of an_receive_idle = true
and link status for the supported link as described in Clause
73.10.1. The following encodings are defined:
• 6'b000000: 1000BASE-KX
• 6'b000001: 10GBASE-KX4
• 6'b000100: 10GBASE-KR
• 6'b001000: 40GBASE-KR4
• 6'b010000: 40GBASE-CR4
• 6'b100000: 100GBASE-CR10
0x4C3
15:0 RW
User base page low
The Auto Negotiation TX state machine uses these bits if the
Auto Negotiation base pages ctrl bit is set. The following bits
are defined:
• [15]: Next page bit
• [14]: ACK which is controlled by the SM
• [13]: Remote Fault bit
• [12:10]: Pause bits
• [9:5]: Echoed nonce which are set by the state machine
• [4:0]: Selector
Bit 49, the PRBS bit, is generated by the Auto Negotiation TX
state machine.
21:16 RW
Override
AN_TECH[5:0]
AN_TECH value with which to override the current value. The
following bits are defined:
•
Bit-16 = AN_TECH[0]= 1000BASE-KX
•
Bit-17 = AN_TECH[1] = XAUI
•
Bit-18 = AN_TECH[2] = 10GBASE-KR
•
Bit-19 = AN_TECH[3] = 40G
•
Bit-20 = AN_TECH[4] = CR-4
•
Bit-21 = AN_TECH[5] = 100G
You must set 0x4C0 bit-5 for this to take effect .
25:24 RW
Override AN_FEC[1:0] AN_FEC value with which to override the current value. The
following bits are defined:
•
Bit-24 = AN_ FEC [0] = Capability
•
Bit-25 = AN_ FEC [1] = Request
You must set 0x4C0 bit-5 for this to take effect.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
152

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex