2.6.3.8. Design Example
Figure 71. PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side
(1G/10G) Ethernet Channels
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
A10
Reconfiguration
Registers CSR
Avalon-MM Slave
XGMII
CLK FPLL
1G Ref CLK
CMU PLL
10G Ref CLK
ATX PLL
Reset
Control
Reset
Control
Reset
Control
Reset
Control
CH0: PHY_ADDR = 0x0
CH1: PHY_ADDR = 0x1
CH2: PHY_ADDR = 0x2
CH3: PHY_ADDR = 0x3
A10_IP_WRAPPER
XGMII
Source
XGMII
Sink
XGMII
GEN
XGMII
CHK
...
Test Harness
XGMII
Source
XGMII
Sink
XGMII
GEN
XGMII
CHK
...
Test Harness
TH0_ADDR = 0xF nnn
TH1_ADDR = 0xE nnn
Management
Master
JTAG-to-
Avalon-MM
Master
ISSP
Clock and
Reset
A10_DE_WRAPPER
Related Information
• Arria 10 Transceiver PHY Design Examples
• 10-Gbps Ethernet MAC IP Function User Guide.
For more information about latency in the MAC as part of the Precision Time
Protocol implementation.
2.6.3.9. Simulation Support
The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Intel-supported
simulators for this Quartus Prime software release:
• ModelSim Verilog
• ModelSim VHDL
• VCS Verilog
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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