Intel Arria 10 User Manual

Address Bit R/W Name Description
0x464 0 RW
pma_rx_set_locktoda
ta
When set, programs the RX clock data recovery (CDR) PLL
to lock to the incoming data.
0x465 0 RW
pma_rx_set_locktore
f
When set, programs the RX CDR PLL to lock to the reference
clock.
0x466 0 RO
pma_rx_is_lockedtod
ata
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode.
0x467 0 RO
pma_rx_is_lockedtor
ef
When asserted, indicates that the RX CDR PLL is locked to
the reference clock.
2.6.3.7. Creating a 10GBASE-KR Design
Follow these steps to create a 10GBASE-KR design.
1. Generate the 10GBASE-KR PHY with the required parameterization.
The 10GBASE-KR PHY IP core includes a reconfiguration block. The reconfiguration
block provides the Avalon-MM interface to access the PHY registers.
2. Instantiate a reset controller. You can generate a Transceiver Reset Controller IP
core from the IP Catalog. You must connect the Transceiver Reset Controller IP
core and 10GBASE-KR PHY IP core power and reset signals.
3. Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate.
Connect the high speed serial clock and PLL lock signals between 10GBASE-KR
PHY and TX PLLs. For the 1G data rate you can use either fPLL, ATX PLL, or CMU
PLL. For the 10G data rate you can use ATX PLL or CMU PLL.
4. Generate a fPLL to create the 156.25 MHz XGMII clock from the 10G reference
clock.
5.
Use the tx_pma_divclk from the 10GBASE-KR PHY or generate a fPLL to create
the 156.25 MHz XGMII clock from the 10G reference clock.
Unlike in the 10GBASE-KR PHY IP core for Stratix V devices, no Memory
Initialization Files (.mif) are required for the 10GBASE-KR design in Arria 10
devices.
6. Complete the design by creating a top level module to connect all the IP
(10GBASE-KR PHY IP core, PLL IP core, and Reset Controller) blocks.
Related Information
• fPLL on page 359
• CMU PLL on page 368
• ATX PLL on page 350
• Using the Transceiver PHY Reset Controller on page 433
• 10GBASE-KR Functional Description on page 136
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
162

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex