Intel Arria 10 - Page 21

Figure 12. Three-Channel GX Transceiver Bank Architecture
PMA
Channel PLL
(CDR Only)
PCS
Local CGB2
CH2
PMA
Channel PLL
(CMU/CDR)
PCS
Local CGB1
CH1
PMA
Channel PLL
(CDR Only)
PCS
Local CGB0
CH0
FPGA Core
Fabric
Three-Channel GX Transceiver Bank
Master
CGB0
fPLL0
ATX
PLL0
Clock
Distribution
Network
Note: This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
1. Arria
®
10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
21