Intel Arria 10 User Manual

Figure 104. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x1 Mode
CDR
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CDR
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
4
4Master
CGB1
Master
CGB0
6
6
6
6
6
6
X1 Network
ATX PLL1
fPLL1
fPLL0
ATX PLL0
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x1 mode.
2. Gen1/Gen2 modes use the fPLL only.
3. Gen3 mode uses the ATX PLL only.
4. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
5. Select the number of TX PLLs (2) in the Native PHY IP core wizard.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
243

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English