Intel Arria 10 User Manual

Steps to implement a multi-channel xN non-bonded configuration
1. You can use either the ATX PLL or fPLL for multi-channel xN non-bonded
configuration.
• Refer to Instantiating the ATX PLL IP Core on page 354 or Instantiating the
fPLL IP Core on page 362 for detailed steps.
• Because the CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL
can be used for this example.
2. Configure the PLL IP core using the IP Parameter Editor. Enable Include
Master Clock Generation Block .
3. Configure the Native PHY IP core using the IP Parameter Editor
• Set the Native PHY IP core TX Channel bonding mode to Non-Bonded .
• Set the number of channels as per your design requirement. In this example,
the number of channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
•
In this case, the PLL IP core has mcgb_serial_clk output port. This
represents the xN clock line.
•
The Native PHY IP core has 10 (for this example) tx_serial_clk input
ports. Each port corresponds to the input of the local CGB of the transceiver
channel.
•
As shown in the figure above, connect the mcgb_serial_clk output port of
the PLL IP core to the 10 tx_serial_clk input ports of the Native PHY IP
core.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
402

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex