Figure 201. Transmitter and Receiver Reset Sequence
FPGA Device
Power Up/Operation
Ensure Calibration
Completed
PLL,TX/RX Analog
Reset Asserted
Associated PLL/CDR
Locked
Release TX/RX
Digital Reset
TX/RX Reset
Completed
Transmit
or
Receive
1
2
3
5
6
7
4
Wait for required time and all gating
conditions and release PLL/Analog
resets
8
4.3.1.1.1. Resetting the Transmitter During Device Operation
Follow this reset sequence to reset the PLL or the analog or digital blocks of the
transmitter at any point during the device operation. Use this reset sequence to
reestablish a link or after dynamic reconfiguration. The following steps detail the
transmitter reset sequence during device operation. The step numbers correspond to
the numbers in the following figure.
1. Perform the following steps:
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
420
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