Intel Arria 10 User Manual

a.
Assert tx_analogreset, pll_powerdown, and tx_digitalreset while
pll_cal_busy and tx_cal_busy are low.
b.
Deassert pll_powerdown after a minimum duration of 70 μs.
c.
Deassert tx_analogreset. This step can be done at the same time or after
you deassert pll_powerdown.
2.
The pll_locked signal goes high after the TX PLL acquires lock. Wait for a
minimum of 70 μs after deasserting tx_analogreset to monitor the
pll_locked signal.
3.
Deassert tx_digitalreset, after pll_locked goes high. The
tx_digitalreset signal must stay asserted for a minimum t
tx_digitalreset
duration after tx_analogreset is deasserted.
Note:
You must reset the PCS blocks by asserting tx_digitalreset, every time
you assert pll_powerdown and tx_analogreset.
Figure 202. Transmitter Reset Sequence During Device Operation
Device Power Up
pll_cal_busy
tx_cal_busy
tx_analogreset
pll_powerdown
pll_locked
Note:
(1) The Arria 10 Default setting presets tx_digitalreset to 70 μs.
tx_digitalreset
t
req
= 70 μs
(1)
t
tx_digitalreset
t
req
t
req
1 2 3
(2) Area in gray is don’t care logic state.
Related Information
Arria 10 Device Datasheet
4.3.1.1.2. Resetting the Receiver During Device Operation
Follow this reset sequence to reset the analog or digital blocks of the receiver at any
point during the device operation. Use this reset to re-establish a link or after dynamic
reconfiguration.
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
421

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex